The present invention relates to semiconductor technology and, more particularly, to techniques effective for application to a semiconductor integrated circuit provided with DRAMs (dynamic random access memories) and to fabricating such a semiconductor integrated circuit.
The memory cell of a DRAM capable of storing 1 bit of information is a series circuit of a memory cell select MISFET and a capacitor. One of the semiconductor region of the memory cell select MISFET is connected to a complementary data line, and the other semiconductor region is connected to one of the electrodes of the data storage capacitor. The other electrode of the data storage capacitor is held at a predetermined potential.
To provide such a DRAM with a large storage capacity, the components are integrated and the miniaturization of the component memory cells has been desired. Since the data storage capacitors also is miniaturized when the memory cell is miniaturized, the charge storage capacity, i.e., data storage capacity, of the data storage capacitor is reduced involving reduction in the alpha particle soft error immunity of the DRAM. As for DRAMs, particularly DRAMs having a large storage capacity greater than 1M bits, the improvement of alpha particle soft error immunity is one of the important technical subjects.
In view of such a technical subject, the memory cell of recent DRAMs employs a data storage capacitor having stacked structure (hereinafter referred to as "stacked data storage capacitor"). The stacked data storage capacitor is constructed by sequentially stacking a lower electrode layer, a dielectric film and an upper electrode layer. Part of the lower electrode layer is connected to one of the semiconductor regions of the memory cell select MISFET, and the other region of the lower electrode layer is extended on a gate electrode. The lower electrode layer is formed in a predetermined pattern by etching a polycrystalline silicon film deposited by a CVD process through a photolithographic etching process. The dielectric film is formed on the upper and side surfaces of the lower electrode layer. The upper electrode layer is formed on the surface of the dielectric layer. The stacked data storage capacitors of the adjacent memory cells use a single upper electrode layer in common as a common plate electrode. The upper electrode layer is formed, similarly to the lower electrode layer, of a polycrystalline silicon layer.
A DRAM having memory cells employing stacked data storage capacitors is disclosed in U.S. Pat. No. 07/246,514 corresponding to Japanese Pat. Application No. 62-235906.